Silicon carbide (SiC), as compared with silicon (Si), possesses excellent physical properties, such as a wide band gap and large dielectric breakdown strength. By using silicon carbide (SiC) as a substrate material, therefore, it is made feasible to fabricate a power semiconductor device of high blocking voltage and low resistance that surpass the limits of silicon (Si).
Further, silicon carbide (SiC) is characterized, similarly to silicon (Si), by being capable of forming an insulating film by thermal oxidation. For this reason, it is inferred that a MOSFET of high blocking voltage and low on-resistance that uses silicon carbide (SiC) as a substrate material can be realized. Thus, many researches and developments directed toward this realization are now under way.
The developments of MOSFETs promoted to date have been performed on the (0001) plane because of the availability of epitaxial wafer that is excellent in crystallinity and comparatively inexpensive. On this plane, however, the MOS interface reveals low mobility of channel and renders a decrease of on-resistance difficult. In contrast, it has been reported as disclosed in Non-Patent Document 1 that on the (000-1) plane which is the back surface of the (0001) plane, the channel mobility of the MOS interface is greatly affected by the atmosphere of thermal oxidation and it exhibits a larger value than on the (0001) plane when the oxidation is performed in a wet atmosphere. It is, therefore, expected that the use of this plane will enable realization of a MOSFET of low on-resistance.
For the sake of enabling a silicon carbide MOSFET to decrease on-resistance and stabilize a structure of blocking voltage, the formation of ohmic contact proves to be an important technique. Particularly, since a p-type impurity element shows a low ratio of activation to a p-type region, no ohmic contact is derived from mere deposition of a metal. Generally, as disclosed in Non-Patent Document 2, for example, a technique for forming a reaction layer of metal and silicon carbide by implementing vapor deposition of the metal and subsequently annealing the resultant composite in argon at 1000° C. has been in use. Then, this method that is capable of acquiring ohmic contact with a p-type region has been being used in the semiconductor devices like a vertical MOSFET which form ohmic contact through both the n type and p type of minute contact holes in the surface.
FIG. 8 is a drawing depicting the dependency of channel mobility on gate voltage in a horizontal MOSFET fabricated on a silicon carbide p-type substrate.
FIG. 8(a) and FIG. 8(b) depict formations of gate oxide film by wet oxidation at 1200° C. using the (0001) plane. FIG. 8(c) and FIG. 8(d) depict formations of gate oxide film by wet oxidation at 900° C. using the (000-1) plane. The ohmic contacts with the n-type source and drain regions in FIG. 8(a) and FIG. 8(c) are formed solely by vapor deposition of aluminum and those in FIG. 8(b) and FIG. 8(d) are formed by vapor deposition of nickel and subsequent annealing in an atmosphere of argon at 1000° C. for 2 minutes. The ohmic contacts with the p-type regions are obtained from the whole back surfaces of substrates. As regards characteristics, first on the (0001) plane, low channel mobility of about 10 cm2/Vs is exhibited no matter whether ohmic contact anneal is present or absent. Meanwhile on the (000-1) plane, in FIG. 8(c) wherein anneal is absent, the electric current between the source and the drain is increased and the channel mobility is maximized to such a high level as about 88 cm2/Vs when the gate voltage is increased and in FIG. 8(d) wherein anneal is present, the channel mobility is zero and absolutely no electric current flows without reference to the gate voltage.
Thus, the channel property of the MOSFET is conspicuously degraded by the ohmic contact anneal on the (000-1) plane, while it is not affected by the anneal on the (0001) plane. Consequently, the problem that the technique optimized on the (0001) plane will not be applicable to the (000-1) plane may arise.
Though the cause of this problem has not yet been elucidated in detail, the problem may be explained by supposing that when the oxidation is performed in a wet atmosphere, the efficiency with which hydrogen terminates interface level is higher on the (000-1) plane than on the (0001) plane and consequently the channel mobility is proportionately heightened but that when the anneal is implemented subsequently in an inert gas, hydrogen is easily desorbed from the interface level.
Non-Patent Document 1: Fukuda et al., Applied Physics Letters, Vol 84, pp. 2088-2090
Non-Patent Document 2: Tanimoto et al., Materials Science Forum, Vols. 389-393, pp. 879-884